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DARPA Targets Reconfigurable Computing Hardware

July 25, 2018

At DARPA ERI Summit, academic and commercial industry research groups named to explore how novel compute architectures can halt threats to U.S. microelectronics

The general-purpose computer has remained the dominant computing architecture for the last 50 years, driven largely by the relentless pace of Moore’s Law—the transistor-scaling that has allowed for a half-century of rapid progress in electronics. As this trajectory shows signs of slowing, however, it has become increasingly more challenging to achieve performance gains from generalized hardware, setting the stage for a resurgence in specialized architectures.

During the ERI Summit in San Francisco, California, hundreds of members of the electronics community convened to discuss the future of the U.S. semiconductor industry. On the first day of the Summit, DARPA unveiled the research teams selected to take on six new ERI "Page 3" programs and keynote speakers addressed the critical role public/private partnerships can play in the innovation cycle.

The program managers behind DARPA’s Electronics Resurgence Initiative (ERI) have selected research teams from academia and industry to explore the development of flexible architectures capable of using specialized hardware to solve specific computing problems more quickly and efficiently. As a part of the ERI Architectures research thrust area, the list of research teams selected for the Software Defined Hardware (SDH) program include Intel, NVIDIA, Qualcomm, Systems & Technology Research (STR), Georgia Institute of Technology, Stanford University, University of Michigan, University of Washington, and Princeton University. Under the Domain-specific System on Chip (DSSoC) program, selected research teams include IBM, Oak Ridge National Labs, Arizona State University, and Stanford University.

DARPA announced the SDH and DSSoC research teams yesterday during the first annual ERI Summit in San Francisco, California. The three-day event has brought together hundreds of members of the electronics community to explore the future of the industry and the impact on national defense that this critical sector plays.

Launched in September 2017, SDH and DSSoC are two of six ERI “Page 3” programs—so named for their relevance to the guidance shared by Gordon Moore on the third page of his seminal 1965 research paper that articulated the technology trend which became known as Moore’s Law. Designed to fulfill the post-scaling predictions made by Moore, the ERI “Page 3” Architectures programs seek to answer: Can we enjoy the benefits of specialized and application-reconfigurable circuitry while still relying on general programming constructs through integrated software/hardware co-design?

The SDH and DSSoC programs seek to explore new ways to co-optimize software and hardware without requiring more complex programming. Both programs aim to prove that there need not be a continued tradeoff between efficiency, like that found in application-specific integrated circuits (ASICs)—that is, hardware customized for a specific application—and flexibility, the hallmark of general-purpose processors.

The SDH program aims to develop hardware and software that can be reconfigured in real-time based on the data being processed, adapting the computing architecture for the workload and data at hand. To achieve this goal, researchers will investigate reconfigurable computing architectures and software environments that can deliver specialized, data-intensive application performance without sacrificing versatility or programmability, and without the need to develop specialized circuits for each application. If successful, SDH could open a pathway to data-intensive algorithms that can run at very low cost, ultimately enabling the widespread use of machine learning and AI for DoD applications like predictive logistics and decision support, as well as intelligence, surveillance, and reconnaissance (ISR) functions.

“The ability to understand data and predict the world around us delivers a fundamental advantage for human nature and can lead to an asymmetric advantage for the DoD,” said Wade Shen, the program manager leading SDH who bridges the gap between hardware and software by working across DARPA’s Microsystems Technology Office (MTO) and Information Innovation Office (I2O). “For problems that cannot afford the large investment required for fully custom solutions, we currently sacrifice compute efficiency by implementing solutions in the form of software on general-purpose processors or field-programmable gate arrays (FPGAs). Often, this results in application implementations that are less than optimal. SDH will develop runtime-reconfigurable hardware and software that enables near full-custom performance without sacrificing programmability for data-intensive algorithms, enabling efficient processing implementations with a single architecture and shared software environment.”

To further address the tradeoff between processor flexibility and efficiency, the second program under the Architectures research thrust area seeks to develop a method for determining the right amount and type of hardware specialization while making a system as programmable and flexible as possible. The DSSoC program aims to enable the rapid development of multi-application systems through a single programmable framework. Such a framework would enable System on Chip (SoC) designers to mix and match general purpose, special purpose (e.g., ASICs), and hardware accelerator coprocessors into easily programmed SoCs for applications within specific technology domains.

The first domain that DSSoC researchers will explore is software-defined radio, a technology with roles in mobile and satellite communications, personal area networks, radar, and electronic warfare.

“It is critical for the DoD to have flexible, adaptable radio systems that are capable of managing and combating a complex signal environment,” said Tom Rondeau, the Microsystems Technology Office program manager leading DSSoC. “These devices must be programmable like general purpose processors, but also capable of crunching a lot of math with low power. The concept of mixing processor cores to achieve a needed level of specialization is an exciting prospect, but without the ability to enable the developer to program for these devices, their utility is limited. DSSoC is looking to address the right levels of heterogeneous processing, while simultaneously focusing on the software tools and supporting the developer ecosystem surrounding software-defined radio initially and expanding beyond that throughout the program.”

ERI is a five-year, upwards of $1.5 billion investment to jumpstart innovation in the electronics industry. To address the impending engineering and economic challenges confronting those striving to push microelectronics technology forward, DARPA is nurturing research in systems architectures, advanced new materials, and circuit design tools through a mix of new and emerging programs.

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