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Intel Touts Advancements at Open Compute Project Global Summit

March 15, 2019

At the Open Compute Project (OCP) Global Summit, Intel today announced new open hardware advancements enabling greater computing capabilities, innovation and cost efficiencies for data center hardware developers. The new advancements include a high-density, cloud-optimized reference design; collaboration with Facebook on the upcoming Intel Cooper Lake processor family; and optimization on Intel’s Rack Scale Design.

“OCP is a vital organization that brings together a fast-growing community of innovators who are delivering greater choice, customization and flexibility to IT hardware. As a founding member of this open source community, Intel is committed to delivering innovative products that help deploy infrastructure underlying the services that support the digital economy.”
–Jason Waxman, Intel corporate vice president, general manager and data-centric chief strategy officer

Why It’s Important: The rise of artificial intelligence (AI), the internet of things (IoT), the cloud and network transformation are creating massive amounts of largely untapped data. Since the inception of OCP, the workloads and deployment models driving data center infrastructure have changed dramatically. In the move to a more data-centric world, homogenous infrastructure in data centers is being replaced by workload-optimized systems. Both OCP and Intel are committed to designing hardware that is uniquely equipped to handle this unprecedented scale in the most efficient way.

What is Intel’s Role: Today’s announcements will enable greater flexibility, customization and efficiency for the OCP community. Intel’s engineering expertise will help drive the future of computing and will deliver the products and technologies that are the foundation for innovation.

What It Delivers:

  • The first high-density, cloud-optimized reference design: A new cloud-optimized, 4-socket reference design offered for next-generation Intel® Xeon® Scalable processors will increase core count up to 112 in a single 2U platform, increase memory bandwidth and provide potential double-digit total cost of ownership savings. Designed for cloud IaaS, Bare Metal and function-as-a service solutions, this new design is jointly contributed to OCP by Intel and Inspur, as an Open Accepted Certified submittal. Dell, HP, Hyve Solutions, Lenovo, Quanta, Supermicro, Wiwynn and ZT Systems are expected to deliver solutions based on this reference design in 2019.
  • Intel and Facebook collaborate on Cooper Lake design: A collaboration based on Intel’s upcoming Cooper Lake 14nm Intel Xeon® processor family will feature Bfloat 16, a 16-bit floating point representation for deep learning training. Bfloat 16 improves performance by offering the same dynamic range as the standard 32-bit floating point representations, accelerating AI deep learning training for various workloads such as image-classification, speech-recognition, recommendation engines and machine translation.
  • Rack Scale Design refresh: Intel will contribute its RSD 2.3 Rack Management Module code to the newly formed OCP-based community, OpenRMC. With more than a year in development, Intel is aligning efforts to drive simple common standards for BIOS, baseboard management controller (BMC), and rack management software through its engagement in the OCP system, OpenBMC and OpenRMC firmware projects.
  • OCP-compliant NIC’s: Intel will release a complete family of OCPv3.0-complaint network interface controllers (NIC) ranging from 1GbE to 100GbE (1, 10, 25, 50, 100) starting mid-year. This will include next-generation Intel Ethernet with new features for application performance scalability, predictability and programmable pipeline architecture.

Also, The Linux Foundation noted its intent to form the CHIPS Alliance project to host and curate high-quality open source code relevant to the design of silicon devices. CHIPS Alliance will foster a collaborative environment that will enable accelerated creation and deployment of more efficient and flexible chip designs for use in mobile, computing, consumer electronics, and Internet of Things (IoT) applications.

Early CHIPS Alliance backers include Esperanto Technologies, Google, SiFive and Western Digital, all committed to both open source hardware and continued momentum behind the free and open RISC-V architecture.

“The RISC-V community is working to foster open source foundation technologies that will help unlock market innovation to move [artificial intelligence/machine learning and infrastructure composability] forward,” said Eric Burgener, research vice president of IDC’s Infrastructure Systems, Platforms, and Technologies Group, via a recent IDC report.

The project will create an independent entity so companies and individuals can collaborate and contribute resources to make open source CPU chip and system-on-a-chip (SoC) design more accessible to the market.

“Open collaboration has repeatedly proven to help industries accelerate time to market, achieve long-term maintainability, and create de facto standards,” said Mike Dolan, vice president of strategic programs, the Linux Foundation. “The same collaboration model applies to the hardware in a system, just as it does to software components. We are eager to host the CHIPS Alliance and invite more organizations to join the initiative to help propel collaborative innovation within the CPU and SoC markets.”

“As new workloads surface every day, we need new silicon designs in order to optimize processing requirements,” said Martin Fink, interim CEO of RISC-V Foundation and executive vice president and CTO of Western Digital. “Today’s legacy general-purpose architectures are, in some cases, decades old. With the creation of the CHIPS Alliance, we are expecting to fast-track silicon innovation through the open source community.”

CHIPS Alliance will follow governance practices consistent with other Linux Foundation projects, which will include a Board of Directors, a Technical Steering Committee, and community contributors who will work collectively to manage the project. Initial plans will focus on establishing a curation process aimed at providing the chip community with access to high-quality, enterprise grade hardware.

PLANNED CONTRIBUTIONS

Google
Google is planning to contribute a Universal Verification Methodology (UVM)-based instruction stream generator environment for RISC-V cores. The environment provides configurable, highly stressful instruction sequences that can verify architectural and micro-architectural corner-cases of designs.

SiFive
SiFive was founded by the inventors of the free and open RISC-V Instruction Set Architecture, who, together with their colleagues at UC Berkeley, developed the first opensource RISC-V microprocessors and a new opensource hardware description language Chisel. This initial work at UC Berkeley also developed the RocketChip SoC generator, including the initial version of the TileLink coherent interconnect fabric.

SiFive remains committed to maintaining and improving the RocketChip SoC generator and the TileLink interconnect fabric in opensource as a member of the CHIPS Alliance, and contributing to Chisel and the FIRRTL intermediate representation specification and transformation toolkit. SiFive will also contribute and maintain Diplomacy, the SoC parameter negotiation framework.

Western Digital
Western Digital is planning to contribute their high performance, 9-stage, dual issue, 32-bit SweRV Core, together with a test bench, and high-performance SweRV Instruction set simulator. Additional contribution will be specification and early implementations of OmniXtend cache coherence protocol.

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