Cisco Silicon One Easily Shatters the 25.6T Barrier By Rakesh Chopra, Cisco March 12, 2021
Back in December of
2019, we made a
bold announcement
around how we’ll forever change the economics of the Internet and drive
innovation at a speed like no one had ever seen before. These were ambitious
claims, and not surprisingly many people took a wait-and-see attitude. But in
October of 2020, we
announced
six new devices where we expanded the Cisco Silicon One platform from a
primarily routing-focused solution to one which also addresses the web scale
switching market. Today,
less than five months from our last announcement, I’m pleased to
introduce three new members of the Cisco Silicon One family which bring
us to a total of 10 devices in less than 15 months. With this
announcement, Cisco Silicon One now provides both the highest bandwidth
routing and web scale switching silicon in one unified family. This pace
of innovation is a testament to the investments we’ve made over the last
six years to create the first truly scalable and multi-purpose platform
in the industry. The Cisco Silicon One
G100
brings the benefits of our unified architecture to the next level with
the industry’s first 25.6Tbps programmable and fully shared packet
buffered device in 7nm. By extending the Cisco Silicon One family to
25.6Tbps, Cisco now provides the leading routing and web scale switching
silicon. With this new device, customers no longer need to choose
between programmability, bandwidth, and efficiency. Cisco Silicon One now
provides the highest bandwidth routing and switching silicon in a
unified family. By further optimizing the
efficiency of our run-to-completion engines for switching, we can
provide programmability with little to no power and performance
tradeoff. Additionally, our unique processor allows for extensive and
extendable visibility, creating the industry’s first programmable
telemetry processor. By combining many
programmable functions like parsing, processing, timestamping, counters,
meters, histograms, watermarks, and flow analytics we’ve created a fully
programmable temporal view of traffic patterns. Done in nano-second (nSec)
granularity, this programmable infrastructure allows customers to replay
past events to truly understand the dynamics of their networks to
troubleshoot the equipment, optimize the infrastructure, and identify
malicious attacks. With the industry’s first
1.6Tbps interface and a four times speed increase over today’s deployed
400GE interfaces, Cisco Silicon One G100 allows customers to scale-up
their networks in ways that were previously impossible. Because of the
innovative packet processing engines, the G100 can even process a single
flow at the full 1.6Tbps. Using 256x112G
exceptional performance LR PAM4 SerDes with our incredibly low-power
architecture, together with our system-first silicon design methodology,
customers can build a 32x800G retimer-less 1RU system while still
allowing for passive Direct Attach Copper (DAC) cables to be used within
the rack, driving a new level of efficiency into their networks. To
enable massive scale-out networks the G100 provides an ethernet Media
Access Control (MAC) for every SerDes, allowing customers to deploy a
truly scaled-out 256x100GE architecture with a single piece of silicon. As networking speeds
increase, the Cisco Silicon One fully shared packet buffer plays an
increasingly important role in the network. Arbitrary traffic patterns
flowing through the G100 can access the entire packet buffer, thereby
enabling exceptional network performance under any congestion scenario. The Cisco Silicon One
G100 is sampling to our customers now. Watch the video to learn
more:
The Cisco Silicon One
Q211L
extends our existing 12.8Tbps
Q200L,
6.4Tbps
Q201L,
and 3.2Tbps
Q202L
leaf and Top of Rack (TOR) switches. At 8Tbps with built-in 7nm with
160x56G PAM4 SerDes, customers can build optimized 40x200GE 1RU systems. Like all members of the
Q2 family, the Q211L enables customers to simplify their network design
with large scale tables and support for advanced SmartTOR features
Network Address Translation (NAT) and Port Address Translation (PAT)
using our highly efficient run-to-completion P4 processors. Customers
can optimize their network performance by using our advanced
hierarchical traffic manager, fully shared packet buffering, and
hierarchical Equal-Cost Multi-Path (ECMP) engines. The Cisco Silicon One
Q211L, like its other Q2 family members, is in full production. The Cisco Silicon One
Q200 extends our existing 8Tbps
Q200,
6.4Tbps
Q201
and 3.2Tbps
Q202
routing devices. At 8Tbps, with built-in 7nm with 160x56G PAM4 SerDes,
customers can build optimized fixed systems with a combination of 10GE
to 400GE ports. The Q211 enjoys all the
same benefits as the Q211L in a foot-print compatible package but adds
even larger table scale and deep packet buffers for routing
applications.
But what excites me the
most today is that this pace of innovation we’ve demonstrated is not
slowing down. In fact, it’s increasing. Over the last six years we’ve
laid the foundation for the next several decades of networking and are
now starting to see what’s possible with the right investment, the right
technology, and the right team. Stay tuned for more! |
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