DARPA Taps Intel for SAHARA

March 23, 2021

DARPA introduced the Structured Array Hardware for Automatically Realized Applications (SAHARA) program, which aims to expand access to domestic manufacturing capabilities to tackle challenges hampering the secure development of custom chips for defense systems. Working in partnership with Intel and academic researchers from University of Florida, University of Maryland, and Texas A&M, SAHARA will leverage leading-edge, U.S.-based manufacturing capabilities to enable the automated and scalable conversion of defense-relevant field-programmable gate array (FPGAs) designs into quantifiably secure Structured ASICs. The program will also explore novel chip protections to support the manufacturing of silicon in zero-trust environments.

SAHARA is a critical program supporting the Department of Defense (DoD) microelectronics Roadmap led by the Under Secretary of Defense for Research and Engineering – USD(R&E) – to define, quantify, and standardize security while strengthening domestic semiconductor manufacturing. The Rapid Assured Microelectronics Prototypes-Commercial (RAMP-C) and State-of-the-Art Heterogeneous Integration Prototype (SHIP) projects are also integral to the DoD Roadmap.

According to USD(R&E), it is critical that the DoD partners with leading U.S. semiconductor companies. The DoD microelectronics Roadmap recognizes the importance of partnerships with industry, and also prioritizes and recognizes that the DOD must have access to state-of-the-art capabilities. SAHARA directly contributes to advancing the objectives outlined in the DoD Roadmap and further strengthens the DoD partnership with Intel, a world leader in this technology.

While FPGAs are widely used in military applications today, Structured ASICs deliver significantly higher performance and lower power consumption, which makes them an efficient and effective alternative for defense electronic systems. Manually converting FPGAs to Structured ASICs, however, is a complex, lengthy, and costly process, making it difficult to justify the economic burden at the volume of custom chips required by DoD applications. Further, current conversion processes do not address design security considerations. To dramatically shorten the design process, reduce associated engineering costs, and enhance chip security, the Intel team will work to automate the conversion process for both currently fielded FPGAs as well as future capabilities, while adding unique chip protections to address supply chain security threats.

“The structured ASIC platforms and methods developed in SAHARA together with the advanced packaging technology developed in SHIP will enable the U.S. Department of Defense to more quickly and cost effectively develop and deploy advanced microelectronic systems critical to DoD modernization priorities,” said Brett Hamilton, deputy principal director for Microelectronics in USD(R&E).

Additionally, Intel aims to establish domestic manufacturing capabilities for the Structured ASICs on their 10nm process. The partnership enables the use of leading-edge foundry capabilities for the development of secure military electronics – something not currently available on-shore.

“SAHARA aims to enable a 60 percent reduction in design time, a 10X reduction in engineering costs, and a 50 percent reduction in power consumption by automating the FPGA-to-Structured ASICs conversion,” said Serge Leef, a program manager in DARPA’s Microsystems Technology Office. “The partnership with Intel will ultimately afford the DoD with significant cost and resource savings while enabling the use of leading-edge microelectronics across a host of applications.”

To bolster chip security, SAHARA is also exploring security countermeasures capable of thwarting reverse engineering and counterfeiting attacks. The research teams aim to develop novel chip protections and employ verification, validation, and red teaming to stress test the resulting measures. Once proven, it is anticipated that the countermeasures will be integrated into Intel’s Structured ASIC design flow.